Blurring an image on a computer is relatively straightforward. The entire image is stored in the computer's memory and a program is run on a processor to blur the pixels. The program typically takes a window of pixels and averages them. This averaged value is the new, blurred pixel.

However, processors are inefficient on Field Programmable Gate Arrays (FPGAs). Furthermore, the image is not stored on the FPGA. Instead, the data is transmitted to the FPGA using a protocol such as USB, PCI Express, or Camera Link. The algorithm to blur pixels is modified as shown in the video. The data is buffered in such a way that the FPGA can process a window of pixels once per clock cycle and produce a blurred pixel. As you can see in the video, not all pixels are valid at every clock cycle. The algorithm acts like an assembly line---a process known as pipelining in computing.

There is an additional complication when working with FPGAs. The data transmitted to the FPGA may not be transmitted fast enough for the FPGA to process. When the FPGA expects data and no data is available, the output of the blur can be incorrect. Thus, it is common practice in hardware engineering to implement a Finite State Machine (FSM) to resolve synchronization problems between the FPGA and the hardware transmitting the data. An FSM works like an air traffic controller for airplanes. It determines when pixels are available and guides them into the algorithm in much the same way that an air traffic controller locates airplanes and guides them to the airport.